The Bunch of Wires (BoW) specification for Chiplet connection has been released, according to the OCP Foundation, a nonprofit organization that makes hyperscale innovations accessible to every business. A new silicon market and integrated circuit supply chain model can be sparked by the BoW specification, which is the next phase in the OCP Open Domain Specific Architecture (ODSA) Project’s march in that direction.
The BoW physical layer (PHY) specification complements the OCP ODSA Open High Bandwidth Interconnect (OpenHBI) PHY specification addressing High Bandwidth Memory and other parallel bandwidth-intensive use cases. It is geared for System on a Chip (SoC) disaggregation.
“The demand for specialized silicon has been increasing steadily due to workload diversity, such as with the adoption of AI and ML, and we expect this trend to continue for several years,” said Bill Carter, CTO at OCP Foundation. “In response to this demand the OCP recognizes that it must be a catalyst to establish open and standardized Chiplet ecosystems and new markets by investing in Chiplet interconnect technology that will enable composable silicon. The release of the BoW specification is an important step in this direction. We expect to increase our efforts on developing supply chain models for composable silicon.”
The BoW Specification
The ODSA BoW PHY specification is tailored for both commodity (organic laminate) and advanced packaging technologies, allowing for high-performance designs that are both cost- and energy-effective across a variety of process nodes.
The standard was created to support numerous use cases that would result in substantial scale economies. When disaggregating an existing SoC, care was made to impose as few restrictions as possible and to avoid adding necessary functionality in the specification that would complicate design.
At least ten companies, including Samsung and NXP, are already using the BoW specification, which is available to everyone thanks to an open license. It covers more than a dozen different use cases that span 5, 6, 12, 16, 22 and 65nm process nodes and include Chiplet-based networking products, specialized AI silicon, FPGAs, and processors.
“The semiconductor industry continues to innovate in new and exciting directions with multicore application specific SoCs, custom core architectures, deep learning, optical communications, analog processing techniques, RF interfaces, memory architectures and more,” said Tom Hackenberg, Principal Analyst, Computing & Software Semiconductor, Memory and Computing Division, Yole Intelligence. “The new challenge is how to integrate all of these disparate innovations, several of which are not practical to produce at cutting- edge process nodes. Today’s announcement from the OCP ODSA, releasing the Bunch of Wires open-source specification for Chiplet interconnect, supplies a new tool toward expanding innovation in the market. This opens the door to a more competitive landscape and diversity in innovation at varying cadences and is fuel or a healthy industry.”