Astera Labs, a market pioneer for purpose-built connectivity solutions, has announced the expansion of its Cloud-Scale Interop Lab to provide thorough interoperability testing between its Leo Memory Connectivity Platform and a developing ecosystem of top CXL-based CPUs, memory modules, and operating systems.
To verify performance and interoperability between CPUs, Leo Smart Memory Controllers, and a range of memory modules in real-world use scenarios, the Cloud-Scale Interop Lab uses a complete battery of memory stress tests, CXL protocol checks, and electrical robustness measures.
From the physical layer to the application layer, the testing is conducted in four major areas: PCIe electrical, memory, CXL compliance, and system-level testing across thousands of cycles.
“Compute Express Link is proving to be a critical memory interconnect technology in data-centric systems; however, multiple use cases and a fast-growing ecosystem is proving to be a significant challenge for seamless deployment of CXL solutions at scale,” said Casey Morrison, Chief Product Officer (CPO) at Astera Labs. “Building on the success of our Cloud-Scale Interop Lab for Aries PCIe Smart Retimers and learnings from real CXL silicon solutions working on customer platforms, we are excited to partner with industry leaders to implement end-to-end CXL tests and tools to minimize interoperation risk, reduce system development time and costs, and accelerate time-to-market.”
Key Partnerships – Cloud-Scale Interop Lab
Astera Labs is working on interop testing with leading companies in the sector that are providing CPUs and memory modules for the expanding CXL market.
“The CXL Consortium hosts events that test member company products for compliance to our specifications,” said Jim Pappas, Chairman at CXL Consortium. “With its Cloud-Scale Interop Lab, Astera Labs extends that testing with rigorous interoperability tests from the physical level to the system level with a broad range of hosts, memory and operating systems. As a CXL Consortium contributor member, Astera Labs’ vendor-neutral approach will help accelerate the delivery of CXL memory solutions to market.”
“Both standards compliance and plug-and-play capabilities are an important step toward growing the CXL ecosystem. 4th Gen AMD EPYC processors are compatible with CXL 1.1 standards and help to create composable architectures that provide the infrastructure flexibility, security and performance requirements our customer demand,” said Mahesh Wagh, Senior Fellow, Server Systems Architect, AMD. “We applaud Astera Labs for its commitment to interoperability testing and look forward to our continued collaboration toward delivering truly heterogeneous computing.”
“Intel is committed to accelerating the CXL ecosystem,” said Dr. Debendra Das Sharma, Senior Fellow at Intel. “We are looking forward to continuing our collaboration with Astera Labs and participating in its Cloud-Scale Interop Lab so our customers can more easily deploy reliable and interoperable CXL solutions.”
“Micron is delivering memory innovations for the data center that leverage CXL, and we are collaborating with Astera Labs to test our DDR memory solutions in its Cloud-Scale Interop Lab,” said Raj Hazra, SVP and GM of Micron’s Compute and Networking Business Unit. “Together, we are alleviating the memory bandwidth bottleneck and providing interoperable solutions that result in greater flexibility for data center and cloud infrastructure customers.”
“Our broad portfolio of high-performance and high-density DDR5 DRAM unlocks the full potential of CXL-attached memory expansion and pooling for cloud servers,” Hyungsoo Kim, VP and Head of DRAM Application Engineering Group at SK Hynix. “With contributions from both Headquarters and US Engineering Center, SK hynix is excited to partner with Astera Labs to validate our memory in its Cloud-Scale Interop Lab, to enable our customers to gain assurance that our solution will interoperate seamlessly with Astera Labs’ CXL Controller and customers’ CPU of choice.”
