Researchers at IBM managed to attach silicon photonic chips directly onto a processor package promising a faster, cheaper and lower energy future for computing systems, including cloud data centers. These IBM researchers have demonstrated what may be an important step toward commercializing this next generation of computing technology, which uses photons instead of electrons to transport and manipulate information.
The scientists at IBM Research established a method to integrate silicon photonic chips with the processor in the same package, avoiding the need for transceiver assemblies. The new technique, which will be presented 25 March at this year’s OFC Conference and Exposition in Los Angeles, California, USA, should lower the cost, increase the performance and energy efficiency, and limit size of future data centers, supercomputers and cloud systems.
Optical links can transmit more information over larger distances and are more energy efficient than copper-based links. To optimally benefit from this technology, a tight integration of the electrical logic and optical transmission functions is required. The optical chip needs to be as close to the electrical chip as possible to minimize the distance of electrical connection between them. This can only be accomplished if they are packaged together.
“IBM has been a pioneer in the area of CMOS integrated silicon photonics for more than 12 years, a technology that integrates functions for optical communications on a silicon chip,” said Bert Offrein, manager of the photonics group at IBM Research – Zurich. “In addition to the silicon technology advancements at the chip-level, novel system-level integration concepts are also required to fully profit from the new capabilities silicon photonics will bring.”
Optical interconnect technology is currently incorporated into data centers by attaching discrete transceivers or active optical cables, which come in pre-assembled building blocks. The pre-packaged transceivers are large and expensive, limiting their large-scale use, Offrein added. Furthermore, such transceivers are mounted at the edge of the board, resulting in a large distance between the processor chip and the optical components.
Offrein and his IBM colleagues from Europe, the United States and Japan instead proposed an integration scheme in which the silicon photonic chips are treated similarly to ordinary silicon processor chips and are directly attached to the processor package without pre-assembling them into standard transceiver housings. This would improve the performance and power efficiency of the optical interconnects while reducing the cost of assembly. Challenges arise because alignment tolerances in photonics are critical (sub-micron range) and optical interfaces are sensitive to debris and imperfections, thus requiring the best in packaging technology.
Tapering the Silicon Waveguide
The team demonstrated efficient optical coupling of an array of silicon waveguides to a substrate containing an array of polymer waveguides. The significant size difference between the silicon waveguides and the polymer waveguides originally presented a major challenge. The researchers overcame this obstacle by gradually tapering the silicon waveguide, leading to an efficient transfer of the optical signal to the polymer waveguide.
The method is scalable and enables the simultaneous interfacing of many optical connections between a silicon photonic chip and the system. The optical coupling is also wavelength and polarization insensitive and tolerant to alignment offsets of a few micrometers, Offrein said.
“This integration scheme has the potential to massively reduce the cost of applying silicon photonics optical interconnects in computing systems,” Offrein said. Cheaper photonic technology enables its deployment at a large scale, which will lead to computing systems that can process more information at higher performance levels and with better energy efficiency, he explained.
“Such systems will be key for future applications in the field of cloud-computing, big data, analytics and cognitive computing,” added Offrein. “In addition, it will enable novel architectures requiring high communication bandwidth, as for example in disaggregated systems.”