Bit Ninja

Silicon IP and chip provider Rambus (NASDAQ: RMBS) has achieved a record 4 Gbps performance with its Rambus HBM2E memory interface solution consisting of a fully integrated PHY and controller. The performance would meet the terabyte-scale bandwidth needs of accelerators targeting the most demanding AI/ML training and high-performance computing (HPC) applications.

The fully integrated, production-ready Rambus HBM2E memory subsystem runs at 4 Gbps without PHY voltage overdrive. Rambus teamed with SK hynix and Alchip to implement the HBM2E 2.5D system – to validate in silicon the Rambus HBM2E PHY and Memory Controller IP using TSMC’s N7 process and CoWoS (Chip-on-Wafer-on-Substrate) advanced packaging technologies. Co-designing with the engineering team from Rambus, Alchip led the interposer and package substrate design.

Paired with HBM2E DRAM from SK hynix operating at 3.6 Gbps, the solution would be able to deliver 460 GB/s of bandwidth from a single HBM2E device.

“With this achievement by Rambus, designers of AI and HPC systems can now implement systems using the world’s fastest HBM2E DRAM running at 3.6 Gbps from SK hynix,” said Uksong Kang, vice president of product planning at SK hynix. “In July, we announced full-scale mass-production of HBM2E for state-of-the-art computing applications demanding the highest bandwidth available.”

For Mission-critical AI/ML Designs

“With silicon operation up to 4 Gbps, designers can future-proof their HBM2E implementations and can be confident of ample margin for 3.6 Gbps designs,” said Matthew Jones, senior director and general manager of IP cores at Rambus. “As part of every customer engagement, Rambus provides reference designs for the 2.5D package and interposer to ensure first-time right implementations for mission-critical AI/ML designs.”

To sum up, key benefits of the Rambus HBM2E Memory Interface (PHY and Controller) would include:

  • Achieves one of the industry’s highest speeds of 4 Gbps per pin, delivering a system bandwidth of 460 GB from a single 3.6 Gbps HBM2E DRAM 3D device
  • Fully-integrated and verified HBM2E PHY and Controller reduces ASIC design complexity and speeds time to market
  • Includes 2.5D package and interposer reference design as part of IP license
  • Provides access to Rambus system and SI/PI experts helping ASIC designers to ensure maximum signal and power integrity for devices and systems
  • Features LabStation development environment that enables quick system bring-up, characterization and debug
  • Supports high-performance applications including state-of-the-art AI/ML training and high-performance computing (HPC) systems