Rambus HBM3-Ready Memory Subsystem Brings Performance for AI/ML

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Chips and silicon IP provider Rambus, a global company aiming at making data faster and safer, has announced the release of its Rambus HBM3-ready memory interface subsystem consisting of a fully integrated PHY and digital controller.

Supporting data rates up to 8.4 Gigabits per second (Gbps), the Rambus HBM3-Ready Memory Subsystem would enable terabyte-scale bandwidth accelerators for artificial intelligence/machine learning (AI/ML) and high-performance computing (HPC) applications. The new solution can deliver over a terabyte per second of bandwidth, which is more than double that of high-end HBM2E memory subsystems.

“The memory bandwidth requirements of AI/ML training are insatiable with leading-edge training models now surpassing billions of parameters,” said Soo Kyoum Kim, associate vice president, Memory Semiconductors at IDC. “The Rambus HBM3-ready memory subsystem raises the bar for performance enabling state-of-the-art AI/ML and HPC applications.”

Package Reference Designs

Photo Matt Jones, general manager of Interface IP at Rambus
“With the performance achieved by our HBM3-ready memory subsystem, designers can deliver the bandwidth needed by the most demanding designs,” said Matt Jones, general manager of Interface IP at Rambus.

In addition to the fully integrated HBM3-ready memory subsystem, Rambus provides its clients with interposer and package reference designs to speed their products to market.

“With the performance achieved by our HBM3-ready memory subsystem, designers can deliver the bandwidth needed by the most demanding designs,” said Matt Jones, general manager of Interface IP at Rambus. “Our fully-integrated PHY and digital controller solution builds on our broad installed base of HBM2 customer deployments and is backed by a full suite of support services to ensure first-time right implementations for mission-critical AI/ML designs.”

To sum up, key features of the Rambus HBM3-ready Memory Interface Subsystem would include:

  • Supports up to 8.4 Gbps data rate delivering bandwidth of 1.075 Terabytes per second (TB/s)
  • Reduces ASIC design complexity and speeds time to market with fully-integrated PHY and digital controller
  • Delivers full bandwidth performance across all data traffic scenarios
  • Supports HBM3 RAS features
  • Includes built-in hardware-level performance activity monitor
  • Provides access to Rambus system and SI/PI experts helping ASIC designers to ensure maximum signal and power integrity for devices and systems
  • Includes 2.5D package and interposer reference design as part of IP license
  • Features LabStation development environment that enables quick system bring-up, characterization and debug
  • Enables the highest performance in applications including state-of-the-art AI/ML training and high-performance computing (HPC) systems
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