Rambus Provides DDR5 Registering Clock Driver at 6400 MT/s

To improve server memory performance, DDR5 memory module (RDIMM) manufacturers now have access to Rambus’ new 6400 MT/s DDR5 Registering Clock Driver (RCD) and sampling. A new level of main memory performance for data center servers is made possible by the Rambus Gen3 6400 MT/s DDR5 RCD. It would offer a 33% improvement in data rate and bandwidth over Gen1 4800 MT/s solutions, according to Rambus.

With optimized latency and power, it would deliver timing settings that have been tuned for increased RDIMM margins.

“Data center workloads have an insatiable thirst for greater memory bandwidth and capacity, and our mission is to advance the performance of server memory solutions that meet this need for each new server platform generation,” said Sean Fan, Chief Operating Officer (COO) at Rambus. “We were first in the industry to 5600 MT/s, and now we have raised the bar with our Gen3 DDR5 RCD capable of 6400 MT/s to support a new generation of RDIMMs for server main memory.”

DDR5 Memory Modules

Sean Fan
“We were first in the industry to 5600 MT/s, and now we have raised the bar with our Gen3 DDR5 RCD capable of 6400 MT/s to support a new generation of RDIMMs for server main memory,” said Sean Fan, COO at Rambus.

For cutting-edge servers to reach a new level of speed, Rambus DDR5 memory interface chips, such as the RCD, Signal Presence Detect (SPD) Hub, and Temperature Sensors, can be crucial. More intelligence is included into the RDIMMs of DDR5 memory, enabling almost twice the data rate and four times the capacity of DDR4 RDIMMs while also boosting memory and power efficiency, according to Rambus.

“DDR5 offers tremendous performance enhancements for computing systems,” said Soo-Kyoum Kim, Vice President, Memory Semiconductors at IDC. “As data center applications accelerate demand for more and more memory bandwidth, it is critical that the DDR5 ecosystem extends performance for the fundamental needs of next-generation data centers.”

Rambus would be well-known for its signal integrity (SI) and power integrity (PI) expertise and has over 30 years of high-performance memory experience. This knowledge would enable DDR5 memory interface chips to transmit clock and command/address signals from the host memory controller to the RDIMMs with greater signal integrity.